verilog code for decoder 2x4

BEHAVIORAL:

module dec(a,b,en,c);
input a,b,en;
output[0:3] c;
reg [0:3] c;
reg s0,s1;
always @(a or b or en)
begin
s0 = ~a;
s1 = ~b;
c[0]=(s0&s1&en);
c[1]=(s0&b&en);
c[2]=(a&s1&en);
c[3]=(a&b&en);
end
endmodule

TEST BENCH:

initializing is automatically done in xilinx 14th version .

en=1'b0;b=1'b0;a=1'b0;

#10 en=1'b0;b=1'b0;a=1'b1;

#10 en=1'b0;b=1'b1;a=1'b0;

#10 en=1'b0;b=1'b1;a=1'b1;

#10 en=1'b1;b=1'b0;a=1'b0;

#10 en=1'b1;b=1'b0;a=1'b1;

#10 en=1'b1;b=1'b1;a=1'b1;

end

      initial begin

$monitor($time,"a=%b,b=%b,En=%b,c=%b",a,b,en,c);

end

endmodule