1x4 demultiplexer

BEHAVIORAL:

module dem(Din,s1,s2,y);
input Din,s1,s2;
output[3:0] y;
reg s3,s4;
reg[3:0] y;
always@(Din) begin
s3=~s1;
s4=~s2;
y[0]=Din&s3&s4;
y[1]=Din&s3&s2;
y[2]=Din&s1&s4;
y[3]=Din&s1&s2;
end
endmodule