mux 4x1

Gate Level :
module mux4_1(
    input a,
    input b,
    input c,
    input d,
    input s0,
    input s1,
    output out
    );
wire s2,s3,x,x1,x2,x3;
not (s2,~s0);
not (s3,~s1);
and z1(x,a,s0);
and z2(x1,b,s1);
and z3(x2,c,s2);
and z4(x3,d,s3);
or z5(out,x,x1,x2,x3);

endmodule

Behavioral :

module mux_4(

    input a,b,c,d,s,s0,

output z);

reg s1,s2,x1,x2,x3,x4,z;

always @(a or b or c or d or s or s0)

 begin

 s1=~s;

 s2=~s0;

 x1=s&a;

 x2=s0&b;

 x3=s1&c;

 x4=s2&d;

 z <= #20 (x1||x2||x3||x4);

 end

 endmodule