Verilog code for 3x8 decoder using enable

behavioral :

module dec_3x8(a,b,c,en,d
    );
input a,b,c,en;
output reg [0:7] d;
reg a0,b0,c0;
always @(a or b or c or en) begin
a0=~a;
b0=~b;
c0=~c;
d[0]=a0&b0&c0&en;
d[1]=a0&b0&c&en;
d[2]=a0&b&c0&en;
d[3]=a0&b&c&en;
d[4]=a&b0&c0&en;
d[5]=a&b0&c&en;
d[6]=a&b&c0&en;
d[7]=a&b&c&en;
end

endmodule

SCHEMATIC: 

FIGURE:

TIMING SCALE:

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