verilog code for 1 bit full adder

BEHAVIORAL:

module flad(
    input a,
    input b,
    input Cin,
    output reg sum,
    output reg Cout
    );
reg s1,s2,s3;
always@(a or b or Cin) begin
s1=a^b;
s2=a&b;
s3=s1&Cin;
Cout=s3||s2;
sum=s1^Cin;
end

endmodule

Verilog code for halfadder

module half(

    input a,

    input b,

    output sum,

    output Cout

    );

reg sum,Cout;

always @(a or b) begin

sum=a^b;

Cout=a&b;

end;

endmodule

schematic: