verilog code for 8x1 mux

Behavioral code:

module mx8x1(a1,b1,c1,e0,e1,e2,e3,e4,e5,e6,e7,out
    );
input a1,b1,c1,e0,e1,e2,e3,e4,e5,e6,e7;
output reg out;
reg a0,b0,c0,d0,d1,d2,d3,d4,d5,d6,d7;
always @(a1 or b1 or c1) begin
a0=~a1;
b0=~b1;
c0=~c1;
d0=e0&a0&b0&c0;
d1=e1&a0&b0&c1;
d2=e2&a0&b1&c0;
d3=e3&a0&b1&c1;
d4=e4&a1&b0&c0;
d5=e5&a1&b1&c1;
d6=e6&a1&b1&c0;
d7=e7&a1&b1&c1;
out=d0||d2||d3||d4||d5||d6||d7;
end

endmodule