D FLIPFLOP

Behavioral :

module Dfp(d,clk,q,q1 );
input d,clk;
output reg q,q1;
always@(clk or d) begin
if (d<=1'b0) begin
q=1'b0;q1=1'b1;
end
else if (d<=1'b1) begin
q=1'b1;q1 =1'b0;
end
end
endmodule

Here i considered reset as q=0 (low)

                                        q1=1 (high)

&

Set  as q=1

          q1=0.

RTL schematic :

Test bench wave form :

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Verilog code for 3x8 decoder using enable

behavioral :

module dec_3x8(a,b,c,en,d
    );
input a,b,c,en;
output reg [0:7] d;
reg a0,b0,c0;
always @(a or b or c or en) begin
a0=~a;
b0=~b;
c0=~c;
d[0]=a0&b0&c0&en;
d[1]=a0&b0&c&en;
d[2]=a0&b&c0&en;
d[3]=a0&b&c&en;
d[4]=a&b0&c0&en;
d[5]=a&b0&c&en;
d[6]=a&b&c0&en;
d[7]=a&b&c&en;
end

endmodule

SCHEMATIC: 

FIGURE:

TIMING SCALE:

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verilog code for 8x1 mux

Behavioral code:

module mx8x1(a1,b1,c1,e0,e1,e2,e3,e4,e5,e6,e7,out
    );
input a1,b1,c1,e0,e1,e2,e3,e4,e5,e6,e7;
output reg out;
reg a0,b0,c0,d0,d1,d2,d3,d4,d5,d6,d7;
always @(a1 or b1 or c1) begin
a0=~a1;
b0=~b1;
c0=~c1;
d0=e0&a0&b0&c0;
d1=e1&a0&b0&c1;
d2=e2&a0&b1&c0;
d3=e3&a0&b1&c1;
d4=e4&a1&b0&c0;
d5=e5&a1&b1&c1;
d6=e6&a1&b1&c0;
d7=e7&a1&b1&c1;
out=d0||d2||d3||d4||d5||d6||d7;
end

endmodule