Behavioral :
module Dfp(d,clk,q,q1 );
input d,clk;
output reg q,q1;
always@(clk or d) begin
if (d<=1'b0) begin
q=1'b0;q1=1'b1;
end
else if (d<=1'b1) begin
q=1'b1;q1 =1'b0;
end
end
endmodule
Here i considered reset as q=0 (low)
q1=1 (high)
&
Set as q=1
q1=0.
RTL schematic :
Test bench wave form :
 |
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