verilog code for 1 bit full adder

BEHAVIORAL:

module flad(
    input a,
    input b,
    input Cin,
    output reg sum,
    output reg Cout
    );
reg s1,s2,s3;
always@(a or b or Cin) begin
s1=a^b;
s2=a&b;
s3=s1&Cin;
Cout=s3||s2;
sum=s1^Cin;
end

endmodule

Verilog code for halfadder

module half(

    input a,

    input b,

    output sum,

    output Cout

    );

reg sum,Cout;

always @(a or b) begin

sum=a^b;

Cout=a&b;

end;

endmodule

schematic:

verilog hdl code for 4x2 parity encoder

module par(d1,d2,d3,y1,y2);
input d1,d2,d3;
output y1,y2;
reg y1,y2;
reg s1;
always @(d1 or d2 or d3) begin
s1=~d2;
y1=d1||d2;
y2=d3||(s1&d1);
end
endmodule

1x4 demultiplexer

BEHAVIORAL:

module dem(Din,s1,s2,y);
input Din,s1,s2;
output[3:0] y;
reg s3,s4;
reg[3:0] y;
always@(Din) begin
s3=~s1;
s4=~s2;
y[0]=Din&s3&s4;
y[1]=Din&s3&s2;
y[2]=Din&s1&s4;
y[3]=Din&s1&s2;
end
endmodule

verilog code for decoder 2x4

BEHAVIORAL:

module dec(a,b,en,c);
input a,b,en;
output[0:3] c;
reg [0:3] c;
reg s0,s1;
always @(a or b or en)
begin
s0 = ~a;
s1 = ~b;
c[0]=(s0&s1&en);
c[1]=(s0&b&en);
c[2]=(a&s1&en);
c[3]=(a&b&en);
end
endmodule

TEST BENCH:

initializing is automatically done in xilinx 14th version .

en=1'b0;b=1'b0;a=1'b0;

#10 en=1'b0;b=1'b0;a=1'b1;

#10 en=1'b0;b=1'b1;a=1'b0;

#10 en=1'b0;b=1'b1;a=1'b1;

#10 en=1'b1;b=1'b0;a=1'b0;

#10 en=1'b1;b=1'b0;a=1'b1;

#10 en=1'b1;b=1'b1;a=1'b1;

end

      initial begin

$monitor($time,"a=%b,b=%b,En=%b,c=%b",a,b,en,c);

end

endmodule

2x1 multiplexer

DATA FLOW

module mux2_1(a,b,s,cout);
input a,b,s;
output cout;
assign cout = ((a&s)||(b&~s));
endmodule

GATE LEVEL:

module mux2_1(a,b,s,cout);
input a,b,s;
output cout;
wire s0,x1,x2;
xor (s0,s);
and a1(x1,a,s);
and a2(x2,b,s0);
or a3(cout,x1,x2);
endmodule

BEHAVIORAL:

module mux2_1(a,b,s,cout);
input a,b,s;
output cout;
wire s0,x1,x2;
reg cout;
always @(a or b or s) begin
s0=~s;
x1=a&s;
x2=b&s0;
cout=x1||x2;
end
endmodule

TEST BENCH:

module mux2_1( );
//inputs
wire a,b,s;
//outputs
reg cout;
//instantiate the unit under test
muxgtlev uut (
.a(a),
.b(b),
.s(s),
.cout(cout)
);

initial begin
#10 a=2'b01;
#20 b=2'b10;
#25 s=2'b11;
end
initial begin
$monitor($time,"a=%b,b=%b,s=%b,cout=%b",a,b,s,cout);
end
     
endmodule

mux 4x1

Gate Level :
module mux4_1(
    input a,
    input b,
    input c,
    input d,
    input s0,
    input s1,
    output out
    );
wire s2,s3,x,x1,x2,x3;
not (s2,~s0);
not (s3,~s1);
and z1(x,a,s0);
and z2(x1,b,s1);
and z3(x2,c,s2);
and z4(x3,d,s3);
or z5(out,x,x1,x2,x3);

endmodule

Behavioral :

module mux_4(

    input a,b,c,d,s,s0,

output z);

reg s1,s2,x1,x2,x3,x4,z;

always @(a or b or c or d or s or s0)

 begin

 s1=~s;

 s2=~s0;

 x1=s&a;

 x2=s0&b;

 x3=s1&c;

 x4=s2&d;

 z <= #20 (x1||x2||x3||x4);

 end

 endmodule

XOR verilog HDL code

dataflow:

module sw(
    input a,
    input b,
    output c
    );
assign c= a^b;

endmodule

Behavioral :
module sw(
    input a,
    input b,
    output c
    );
reg c;
always @(a or b) begin
c=a^b;
end
endmodule